NDLI: Survey on memory management techniques in heterogeneous computing systems

Please wait, while we are loading the content...

Survey on memory management techniques in heterogeneous computing systems

Content Provider	IET Digital Library
Author	Hazarika, Anakhi Poddar, Soumyajit Rahaman, Hafizur
Abstract	A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory creates a major bottleneck in overall system performance. The CPU/GPU processes all the data on a computer's memory and hence the speed of the data movement to/from memory and the size of the memory affect computer speed. During memory access by any processing element, the memory management unit (MMU) controls the data flow of the computer's main memory and impacts the system performance and power. Change in dynamic random access memory (DRAM) architecture, integration of memory-centric hardware accelerator in the heterogeneous system and Processing-in-Memory (PIM) are the techniques adopted from all the available shared resource management techniques to maximise the system throughput. This survey study presents an analysis of various DRAM designs and their performances. The authors also focus on the architecture, functionality, and performance of different hardware accelerators and PIM systems to reduce memory access time. Some insights and potential directions toward enhancements to existing techniques are also discussed. The requirement of fast, reconfigurable, self-adaptive memory management schemes in the high-speed processing scenario motivates us to track the trend. An effective MMU handles memory protection, cache control and bus arbitration associated with the processors.
Starting Page	47
Ending Page	60
Page Count	14
ISSN	17518601
Volume Number	14
e-ISSN	1751861X
Issue Number	Issue 2, Mar (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cdt/14/2
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cdt.2019.0092
Journal	IET Computers & Digital Techniques
Publisher Date	2019-12-19
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Big Data Cache Control Cache Storage Computer Architecture CPU/GPU Processes Data Flow Data Scientists Today DRAM Architecture DRAM Chips Dynamic Random Access Memory Architecture File Organisation Graphics Processing Units Heterogeneous Computing System Heterogeneous System High-performance Computing WorkLoad High-speed Processing Scenario HPC WorkLoad Large-scale Parallel Computing Memory Access Time Memory Management Technique Memory Management Unit Memory Protection Memory-centric Hardware Accelerator MMU Control Multiple Graphics Processing Units Multiprocessing System Off-chip Memory Parallel Architecture Parallel Processing PIM System Processing Infrastructure Processing-in-memory Resource Management Technique Self-adaptive Memory Management Scheme
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Cache Coherence for GPU Architectures

Locality-protected cache allocation scheme with low overhead on GPUs

Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality

XY -Type GPU Cache: Exploiting Spatial Localities in both X and Y Directions to Avoid Conflict Miss

The GPU Computing Era

Achieving Exascale Capabilities through Heterogeneous Computing

CUDA memory optimisation strategies for motion estimation

BAG: Managing GPU as Buffer Cache in Operating Systems

Suitability Analysis of FPGAs for Heterogeneous Platforms in HPC

Survey on memory management techniques in heterogeneous computing systems

Similar Documents

Cache Coherence for GPU Architectures

Locality-protected cache allocation scheme with low overhead on GPUs

Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality

XY -Type GPU Cache: Exploiting Spatial Localities in both X and Y Directions to Avoid Conflict Miss

The GPU Computing Era

Achieving Exascale Capabilities through Heterogeneous Computing

CUDA memory optimisation strategies for motion estimation

BAG: Managing GPU as Buffer Cache in Operating Systems

Suitability Analysis of FPGAs for Heterogeneous Platforms in HPC

Survey on memory management techniques in heterogeneous computing systems