NDLI: Hardware-efficient slope-error algorithm based PAM4 baud rate CDR scheme for 40 Gb/s receiver

Content Provider	IET Digital Library
Author	Shi, Linqi Gai, Weixin Tang, Liangxiao Xiang, Xiao He, Ai
Abstract	A hardware-efficient slope-error (SE) algorithm based four-level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC-768 JTOL mask by at least 0.35 UI at the bit error rate of 10−12. The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm2.
Starting Page	1020
Ending Page	1022
Page Count	3
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 17, Aug (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/17
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.1280
Journal	Electronics Letters
Publisher Date	2018-08-06
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Adaptive Decision Feedback Equalisation Adaptive Equalisers Adjacent Data Information Analogue Circuit Baud Rate CDR Bit Error Rate Bit Rate 40 Gbit/s CDR Loop Clock And Data Recovery Circuit CMOS Integrated Circuit CMOS Process Decision Feedback Equalisers Demodulator Discriminators And Mixers Efficiency 36 Percent Error Samplers Four-level Pulse Amplitude Modulation Baud Rate Clock And Data Recovery Scheme Hardware-efficient Slope-error Algorithm Integrated Circuit Design Jitter Layout Low Power Electronics MM CDR Modelling And Testing Modulator Mueller Müller CDR PAM4 Baud Rate CDR Scheme PAM4 Receiver PD Gain Phase Detector Phase Detector Gain Power 106.0 MW Power Efficiency Pulse Amplitude Modulation Receiver Semiconductor Integrated Circuit Design Simulated Jitter Tolerance Size 55.0 Nm Slope Information SONET OC-768 JTOL Mask Voltage 1.2 V
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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