NDLI: Highly optimised reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI

Content Provider	IET Digital Library
Author	Yasir Wu, Ning Zhang, Xiao Qiang Yahya, Muhammad Rehan
Abstract	Highly optimised reconfigurable hardware architecture is proposed of 64 bit block ciphers MISTY1 and KASUMI for wide-area cryptographic applications. The reconfigurable hardware architecture is comprised of reconfigurable components consisting of FL function, FO/FI function and XOR function designed to perform MISTY1 and KASUMI algorithms round transformation functions. In addition, reconfigurable FO/FI function is adequate to generate MISTY1 extended keys for onward use in MISTY1 round transformation function. The substitution functions S9 and S7 for MISTY1 and KASUMI algorithms are optimised for area and throughput. Common sub-expression elimination for AND-XOR logic combined with permutation/combination technique for AND gates reduces the area considerably, whereas parallel execution improves the throughput. With this design approach, application specific integrated circuit (ASIC) implementations using Synopsys Design Complier, SMIC 0.18 µm at 1.8 V achieved an area of 3481 NAND gates having throughput of 130.2 and 154.56 Mbits/s for MISTY1 and KASUMI, respectively. Synthesised FPGA implementation using Xilinx Artix 7 FPGA yielded an area of 487 configurable logic block (CLB) Slices having throughput of 209.43 and 248.7 Mbits/s for MISTY1 and KASUMI, respectively. Detailed design and performance analysis of reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI for ASIC implementations is described.
Starting Page	10
Ending Page	12
Page Count	3
ISSN	00135194
Volume Number	53
e-ISSN	1350911X
Issue Number	Issue 1, Jan (2017)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/53/1
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2016.3982
Journal	Electronics Letters
Publisher Date	2016-11-30
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	AND Gate AND-XOR Logic Application Specific Integrated Circuit ASIC Implementation Bit Rate 130.2 Mbit/s Bit Rate 154.56 Mbit/s Bit Rate 209.43 Mbit/s Bit Rate 248.7 Mbit/s Block Cipher CLB Slices Cryptographic Application Cryptography Data Security Digital Circuit Design, Modelling And Testing Field Programmable Gate Array FL Function Integrated Circuit Design KASUMI Algorithm Layout Logic And Switching Circuit Logic Circuit Logic Design Method Logic Element Logic Gate MISTY1 Algorithm Modelling And Testing NAND Gate Optimised Reconfigurable Hardware Architecture Permutation-combination Technique Reconfigurable FO-FI Function Round Transformation Function S7 Function S9 Function Semiconductor Integrated Circuit Design Size 1.8 Mum SMIC Synopsys Design Complier Voltage 1.8 V Word Length 64 Bit Xilinx Artix 7 FPGA XOR Function
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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