NDLI: Modelling for triple gate spin-FET and design of triple gate spin-FET-based binary adder

Content Provider	IET Digital Library
Author	Malik, Gul Faroz Ahmad Kharadi, Mubashir Ahmad Parveen, Nusrat Khanday, Farooq Ahmad
Abstract	In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then used to implement 3-input XOR, 3-input XNOR and majority gate functions. The designs of 3-input XOR and majority gates were achieved keeping in view that the sum operation of a 1-bit full adder is obtained through XOR gate and the carry operation of 1-bit full adder is obtained through majority gate. Therefore, for designing a 1-bit full adder, only two spin-FETs will be required which signifies the compact nature of the design. In addition, a 2-bit ripple adder is designed with cascading two 1-bit full-adders. Finally, a comparative analysis of the proposed gates and 1-bit full adder with the reported work and conventional CMOS design was carried out in terms of employed number of devices, power consumption and speed. The analysis shows that proposed gates/adder offer better performance than the reported work and conventional CMOS designs.
Starting Page	464
Ending Page	470
Page Count	7
ISSN	1751858X
Volume Number	14
e-ISSN	17518598
Issue Number	Issue 4, Jul (2020)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/iet-cds/14/4
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/iet-cds.2019.0329
Journal	IET Circuits, Devices & Systems
Publisher Date	2020-01-30
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	2-bit Ripple Adder 3-input XNOR 3-input XOR Adder Cascading Two 1-bit Full-adders Channel Resistance CMOS Integrated Circuit CMOS Logic Circuit Conventional CMOS Design Field Effect Transistors III-V SemiConductor InAs Indium Arsenide Channel-based Triple Gate Spin-FET Model Indium Compound Junction Polarisation Logic And Switching Circuit Logic Circuit Logic Element Logic Gate Majority Gate Optical Computing Technique Optical Logic Optical Logic Device Spin Diffusion Length Triple Gate Spin-FET-based Binary Adder Triple-gate Spin-FET XOR Gate
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Efficient design of coplanar ripple carry adder in QCA

Improving speed of tunnel FETs logic circuits

High-performance single-cycle memristive multifunction logic architecture

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

Design of non-restoring binary array divider in majority logic-based QCA

Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing

A Novel Design Approach for Multi-input XOR Gate Using Multi-input Majority Function

Reconfigurable arithmetic logic unit designed with threshold logic gates

Modelling for triple gate spin-FET and design of triple gate spin-FET-based binary adder

Similar Documents

Efficient design of coplanar ripple carry adder in QCA

Improving speed of tunnel FETs logic circuits

High-performance single-cycle memristive multifunction logic architecture

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

Design of a multilayer five-input majority gate and adder/subtractor circuits in NML computing

Design of non-restoring binary array divider in majority logic-based QCA

Design of adder and subtractor circuits in majority logic-based field-coupled QCA nanocomputing

A Novel Design Approach for Multi-input XOR Gate Using Multi-input Majority Function

Reconfigurable arithmetic logic unit designed with threshold logic gates

Modelling for triple gate spin-FET and design of triple gate spin-FET-based binary adder