NDLI: Low-cost single event double-upset tolerant latch design

Content Provider	IET Digital Library
Author	Jiang, Jianwei Xu, Yiran Ren, Jiangchuan Zhu, Wenyi Lin, Dianpeng Xiao, Jun Kong, Weiran Zou, Shichang
Abstract	This Letter proposes a low-cost, single event double-upset tolerant latch which utilises interlocked nodes to keep data, clock gating (CG) in Muller C-element (MCE) to turn off the storage cell, a three-input MCE to block the soft error from the storage cell and a weak keeper to prevent high impedance state. The storage cell in the proposed latch has better reliability than the conventional triple path dual-interlocked storage cell (TPDICE). Most up-to-date single event double-upset (SEDU) tolerant latches are carried out with too large cost penalties. The proposed one saves up to 93.32% area-power-delay product (APDP) compared with one up-to-date SEDU tolerant latch and even saves 36.36% APDP compared with only single event upset (SEU) tolerant latch in the referential. Simulation results have verified SEU and SEDU tolerance of the proposed latch.
Starting Page	554
Ending Page	556
Page Count	3
ISSN	00135194
Volume Number	54
e-ISSN	1350911X
Issue Number	Issue 9, May (2018)
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/el/54/9
Alternate Webpage(s)	https://digital-library.theiet.org/content/journals/10.1049/el.2018.0558
Journal	Electronics Letters
Publisher Date	2018-03-27
Access Restriction	Open
Rights Holder	© The Institution of Engineering and Technology
Subject Keyword	Area-power-delay Product Clock Gating Digital Circuit Design, Modelling And Testing Flip Flops Logic And Switching Circuit Logic Circuit Logic Design Method Low-cost Single Event Double-upset Tolerant Latch Design Muller C-element Radiation Effect (semiconductor Technology) Radiation Hardening (electronics) Soft Error Up-to-date SEDU Tolerant Latch Up-to-date Single Event Double-upset Tolerant Latches
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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