NDLI: Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing

Content Provider	IEEE Xplore Digital Library
Author	Namba, K. Ikeda, T. Ito, H.
Copyright Year	1993
Abstract	In recent high-density VLSIs, soft errors, particularly single event upsets (SEUs), frequently occur during system operation. In addition, the occurrence of delay faults caused by manufacturing defects is a significant problem. Thus, SEU tolerant design and delay fault testing are of increasing significance. This paper presents two types of SEU tolerant flip-flops (FFs). The proposed FFs tolerate SEUs caused by particles striking feedback loops in the FFs. Moreover, the proposed FFs allow enhanced scan delay fault testing. The proposed FFs are master-slave FFs, and the slave latches are constructed by modifying existing SEU tolerant latches, namely, SEH latches. The two proposed FFs tolerate particles with charges of 370 fC and of 369 fC or lower, whereas an existing SEU tolerant enhanced scan FF, called an ESFF-SEC, tolerates those of 431 fC or lower. Furthermore, the areas of the proposed FFs are 23.1% and 20.5% smaller than that of the ESFF-SEC. The CK-Q delay times are 44.4% and 41.1% shorter than that of the ESFF-SEC. Moreover, the average power consumptions of the proposed FFs during system operations are 55.6% and 53.3% lower than that of the ESFF-SEC.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1265
Ending Page	1276
Page Count	12
File Size	625905
File Format	PDF
ISSN	10638210
Volume Number	18
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Delay Single event upset Circuit faults Latches Circuit testing Very large scale integration Manufacturing Design for testability Indium tin oxide single event upset (SEU) Delay fault testing enhanced scan testing scan flip-flop soft error tolerance
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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