NDLI: Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor

Content Provider	IEEE Xplore Digital Library
Author	Jyh-Shian Wang I-Wei Wu Yu-Sheng Chen Shann, J.J.-J. Wei-Chung Hsu
Copyright Year	2009
Abstract	Reducing program size is a critical issue in manyembedded systems which require more functionalitieswithout increasing the memory size. One of theapproaches is to adopt a mixed-width instruction setarchitecture (ISA) which usually has an instruction setin general formats (usually 32-bit long) as normalinstruction set and an instruction set in shorter format(usually 16-bit long) with limited opcodes and set ofregisters. Traditionally, a code segment can beencoded in only one format, no multiple formatsinterleaved. However, more and more processors useinstruction encoding to indicate the length of eachindividual instruction and take mixed-width ISA intoinstruction-level granularity. For this kind of ISAs, thenumber of instructions can be encoded in shorterformat is highly dependent on the limited set ofregisters that can be accessed by shorter formatinstructions. In this paper, we present a registerallocation and assignment algorithm based on graphcoloring, which uses a heuristic model to find outwhich virtual variables in program should be assignedinto the set of registers accessible by shorterinstructions. The simulation results show that 63.34%of the instructions can be translated into shorterformat on average.
Starting Page	174
Ending Page	181
File Size	337775
Page Count	8
File Format	PDF
ISBN	9781424453344
DOI	10.1109/CSE.2009.100
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-29
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Compiler Instruction sets Thumb Switches Encoding Registers Computer science Reduced instruction set computing Embedded system Mixed-Width ISA Embedded Processor Computer architecture Hardware Register allocation
Content Type	Text
Resource Type	Article

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