NDLI: Support of Paged Register Files for Improving Context Switching on Embedded Processors

Content Provider	IEEE Xplore Digital Library
Author	Chung-Wen Huang Kun-Yuan Hsieh Jia-Jhe Li Jenq Kuen Lee
Copyright Year	2009
Abstract	The increasing number of complex jobs scheduled to execute on embedded systems has increased the importance of fast response times in job scheduling and task switching onembedded processors. This paper addresses the issue of reducing context-switching overhead. We present a novel register file architecture, the paged register file (pRF), that comprises two novel mechanisms for reducing context-switching latency related to the hardware context: the valid-annotated register file and semishadowing. The valid-annotated register file contains valid bits to annotate the used registers, which can be used to reduce register accesses in context switching. Moreover, the utilization of the register file is increased by semishadowing, which allows two threads to share the same register file. Experimental results obtained on the XEEMU platform with the benchmarks, DSPstone, show that support for our proposed pRF design reduces the frequency of context-switching by around 24% and reduces the amount of register movements by 46.9%.
Starting Page	352
Ending Page	357
File Size	808265
Page Count	6
File Format	PDF
ISBN	9781424453344
DOI	10.1109/CSE.2009.368
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-29
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded computing Processor scheduling Embedded system Computer architecture Frequency Hardware Registers Application software Yarn Delay
Content Type	Text
Resource Type	Article

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