NDLI: Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow

Content Provider	IEEE Xplore Digital Library
Author	Bekiaris, D. Economakos, G. Sotiriou-Xanthopoulos, E. Soudris, D.
Copyright Year	2011
Abstract	Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfigurable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. A special case of coarse-grain reconfigurable components are morphable multipliers, which use multiplexers to feed different inputs and form different connection schemes within the data path of conventional multipliers. These connection schemes form different components that can be utilized when the initial multiplier is idle. Morphable components offer performance improvements but the use of extra multiplexers impose power overheads. This paper applies two low-power design techniques, power gating and multi Vth components, for the design of low-power morphable multipliers. Experimentation with these multipliers in a high-level synthesis flow show that they can offer performance, area and power improvements compared to alternative architectures, making them valuable building blocks for hardware synthesis.
Starting Page	428
Ending Page	433
File Size	481370
Page Count	6
File Format	PDF
ISBN	9781457717345
e-ISBN	9780769545516
DOI	10.1109/ReConFig.2011.58
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-30
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiplexing Microprocessors reconfigurable architectures Computer architecture runtime reconfiguration high-level synthesis Hardware Timing Sparks Adders artificial intelligence design automation
Content Type	Text
Resource Type	Article

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