NDLI: Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations

Content Provider	IEEE Xplore Digital Library
Author	Abdelhadi, A. Lemieux, G.G.F.
Copyright Year	2011
Abstract	SRAM-based Field-Programmable Gate Arrays (FPGAs) are configured from off-chip memory through a serial link. Hence, a large configuration bit stream adversely increases off-chip memory size as well as bit stream loading time. The following work proposes a novel method to reduce the number of programming bits required for look-up tables (LUT), thereby reducing overall configuration bit stream size. Alternatively, the identified redundancy may be used to hide watermarking or security data. The proposed method does not affect the critical timing paths, nor does it affect the internal architecture of the LUT. The suggested method eliminates floor(log2(k!)) configuration bits out of the 2^k configuration bits required by a k-input LUT (k-LUT). Hence, a 4-LUT, 5-LUT and 6-LUT only requires 12, 26, and 55 bits, respectively, to be stored in the external configuration bit stream, representing a reduction of 25%, 18.75%, and 14% in LUT configuration bits, respectively. Note the LUTs themselves still contain the full 16, 32, and 64 bits, respectively, but the missing bits are regenerated at bit stream load time. Furthermore, traditional loss less compression methods can still be employed on top of the proposed reduction technique.
Starting Page	20
Ending Page	26
File Size	1835057
Page Count	7
File Format	PDF
ISBN	9781457717345
e-ISBN	9780769545516
DOI	10.1109/ReConFig.2011.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-30
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field-programmable Gate Array (FPGA) Redundancy Loading LUT optimization Logic gates Logic functions Reconfigurable Computing Table lookup Finite element methods Bitsream Compression Field programmable gate arrays
Content Type	Text
Resource Type	Article

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