NDLI: A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

Content Provider	IEEE Xplore Digital Library
Author	Wei He de la Torre, E. Riesgo, T.
Copyright Year	2011
Abstract	In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this proposal is that the EPE can be effectively prevented by using a synchronized non regular precharge network, which maintains identical routing between the original and mirror parts, where costs and design complexity compared with previous EPE-resistant countermeasures are reduced, while security level is not sacrificed. Another advantage for our Precharge Absorbed(PA) - DPL method is that its Dual-Core style (independent architecture for true and false parts) could be generated using partial reconfiguration. This helps to get a dynamic security protection with better energy planning. That means system only keeps the true part which fulfills the normal en/decryption task in low security level, and reconfigures the false parts once high security level is required. A relatively limited clock speed is a compromise, since signal propagation is restricted to a portion of the clock period. In this paper, we explain the principles of PA-DPL and provide the guidelines to design this structure. We experimentally validate our methods in a minimized AES co-processor on Xilinx Virtex-5 board using electromagnetic (EM) attacks.
Starting Page	217
Ending Page	222
File Size	1730958
Page Count	6
File Format	PDF
ISBN	9781457717345
e-ISBN	9780769545516
DOI	10.1109/ReConFig.2011.3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-30
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	DPL (Dual-rail Precharge Logic) AES-128 EPE (Early Propagation Effect) Switches Routing Dual-Core LUT Table lookup Synchronization Delay Logic gates SCA (side channel attack) Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA

Efficient Dual-Rail Implementations in FPGA Using Block RAMs

Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA

Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints

Automatic generation of identical routing pairs for FPGA implemented DPL logic

Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.

BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation

Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

Similar Documents

Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA

Efficient Dual-Rail Implementations in FPGA Using Block RAMs

Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA

Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only)

Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints

Automatic generation of identical routing pairs for FPGA implemented DPL logic

Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.

BCDL: a high speed balanced DPL for FPGA with global precharge and no early evaluation

Successful Attack on an FPGA-based WDDL DES Cryptoprocessor Without Place and Route Constraints.

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations