NDLI: Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function

Content Provider	IEEE Xplore Digital Library
Author	Hori, Y. Hyunho Kang Katashita, T. Satoh, A.
Copyright Year	2011
Abstract	A physical unclonable function (PUF) with a novel hardware architecture called Pseudo-LFSR PUF (PL-PUF) is developed. The structure of the PL-PUF is based on LFSR but it actually is large combinational logic. The long feedback signal of the PL-PUF effectively extracts the device variation, and consequently the output IDs generated in the different devices become completely dissimilar. The advantages of the PL-PUF are that (1) the size of the circuit is small since it simply consists of inverters and a few XOR gates, (2) it efficiently outputs a long-bit ID since all n bits of the ID are simultaneously output from a single n-bit challenge, and (3) the challenge-response mapping of PL-PUF can be easily changed without modifying its hardware structure. The reliability of the PL-PUF is also examined in terms of False Acceptance Rate (FAR) and False Rejection Rate (FRR) through the experimentation using FPGAs. The empirical results show that the intra-device Hamming distance among IDs generated in the same PL-PUF is quite small, the inter-device Hamming distance among IDs in different PL-PUFs is sufficiently large. As a consequent, it is demonstrated that the PL-PUF has quite low FAR/FRR and is quite effective for device identification and other security-sensitive applications. This paper describes the structure of the PL-PUF in detail and presents the experimental results of the performance evaluation using Virtex-5 FPGAs.
Starting Page	223
Ending Page	228
File Size	868750
Page Count	6
File Format	PDF
ISBN	9781457717345
e-ISBN	9780769545516
DOI	10.1109/ReConFig.2011.72
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-30
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Hamming distance Pseudo-LFSR PUF device authentication SASEBO-GII High definition video Reliability Security Virtex-5 FPGA Field programmable gate arrays Clocks Physical Unclonable Function
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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