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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Furuta, T. |
| Copyright Year | 2010 |
| Description | Author affiliation: IBIDEN Co., LTD., 3-200 Gama-cho Ogaki-city Gifu-prefecture Japan (Furuta, T.) |
| Abstract | Advancements and reduced geometries in Si development have significantly impacted package substrate technology. In particular, the reduced die size and consumer applications now require higher routing densities, smaller assembly area and an overall thinner profile for package substrates. In support of the high density requirements and general miniaturization trend, a number of packaging solutions have been adopted, including: migration to FC interconnection, and three dimensional packaging structures such as MCP (multi chip package) and POP (package on package). Along with high routing density, thin package reliability requirements remain high and also pose new challenges. Particularly, three dimensional packaging solutions have reduced the threshold for reliability factors such as drop test and warpage. To support these reliability challenges, new surface treatment and substrate material options have been explored. In support of the above mentioned high density and reliability requirements, IBIDEN proposes the FVC (filled via core) substrate structure. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 441790 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424475933 |
| e-ISBN | 9781424475940 |
| DOI | 10.1109/CPMTSYMPJ.2010.5679661 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-08-24 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Gold Nickel Copper Surface finishing Substrates |
| Content Type | Text |
| Resource Type | Article |
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