NDLI: Bio-inspired NoC fault tolerant techniques

Content Provider	IEEE Xplore Digital Library
Author	Sethi, M.A.J. Hussin, F.A. Hamid, N.H.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Univ. Teknol. PETRONAS, Tronoh, Malaysia (Sethi, M.A.J.; Hussin, F.A.; Hamid, N.H.)
Abstract	The incorporation of processing elements which include processor cores, memories, configurable components and DSP cores on Network on Chip (NoC) have made the communication structure of NoC very complex. To support the complexity of NoC, the physical device sizes are scaled down. However, the interconnects are not scaled at the same rate as the device. Interconnects have contributed to faults, system delay and high power consumptions. Interconnects of NoC are more vulnerable to faults. Many fault tolerant routing techniques have been proposed but they still have the energy, power, congestion problems and they lack the adaptiveness and robustness. In this work, two novel bio-inspired NoC techniques are analyzed. The bio-inspired mechanism of “synaptogenesis” and “sprouting” is adopted in the NoC algorithm and architecture. With the help of this the algorithm is robust and NoC is fault tolerant. In sprouting algorithm, the average throughput and average packet latency was increased by 8.56% and 4.65% respectively while average bandwidth was efficiently utilized by 0.23% as compared to synaptogenesis algorithm. The bio-inspired algorithms improved the average throughput and accepted traffic by 72.12% as compared to the literature technique.
Sponsorship	Malaysia Sect. CAS Chapt.
Starting Page	1
Ending Page	6
File Size	442328
Page Count	6
File Format	PDF
e-ISBN	9781479946532
DOI	10.1109/ICIAS.2014.6869449
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-03
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Fault tolerant Fault tolerance Heuristic algorithms Neurons Fault tolerant systems Bandwidth Network on Chip (NoC) Routing Processing Elements (PE's) Bio-inspired Techniques
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in