NDLI: Pipelined architecture for low density parity check encoder

Content Provider	IEEE Xplore Digital Library
Author	Anggraeni, S. Hussin, F.A. Jeoti, V.
Copyright Year	2012
Description	Author affiliation: Electrical and Electronics Engineering Department, Universiti Teknologi PETRONAS, Bandar Seri Iskandar, 31750 Tronoh, Perak, Malaysia (Anggraeni, S.; Hussin, F.A.; Jeoti, V.)
Abstract	This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design.
Starting Page	831
Ending Page	835
File Size	104980
Page Count	5
File Format	PDF
ISBN	9781457719684
e-ISBN	9781457719677
DOI	10.1109/ICIAS.2012.6306129
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-06-12
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	low density parity check (LDPC) Computer architecture Shift registers Parity check codes Encoding pipelining encoder Pipeline processing Flip-flops architecture
Content Type	Text
Resource Type	Article

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