NDLI: Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs

Content Provider	IEEE Xplore Digital Library
Author	Jafri, S.M.A.H. Tajammul, M.A. Hemani, A. Paul, K. Plosila, J. Tenhunen, H.
Copyright Year	2013
Description	Author affiliation: Univ. of Turku, Turku, Finland (Plosila, J.) \|\| R. Inst. of Technol., Stockholm, Sweden (Jafri, S.M.A.H.; Tajammul, M.A.; Hemani, A.; Paul, K.; Tenhunen, H.)
Abstract	Today, coarse grained reconfigurable architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Each application itself is composed of multiple tasks, spatially mapped to different parts of platform. Providing worst-case operating point to all applications leads to excessive energy and power consumption. To cater this problem, dynamic voltage and frequency scaling (DVFS) is a frequently used technique. DVFS allows to scale the voltage and/or frequency of the device, based on runtime constraints. Recent research suggests that the efficiency of DVFS can be significantly enhanced by combining dynamic parallelism with DVFS. The proposed methods exploit the speedup induced by parallelism to allow aggressive frequency and voltage scaling. These techniques, employ greedy algorithm, that blindly parallelizes a task whenever required resources are available. Therefore, it is likely to parallelize a task(s) even if it offers no speedup to the application, thereby undermining the effectiveness of parallelism. As a solution to this problem, we present energy aware task parallelism. Our solution relies on a resource allocation graphs and an autonomous parallelism, voltage, and frequency selection algorithm. Using resource allocation graph, as a guide, the autonomous parallelism, voltage, and frequency selection algorithm parallelizes a task only if its parallel version reduces overall application execution time. Simulation results, using representative applications (MPEG4, WLAN), show that our solution promises better resource utilization, compared to greedy algorithm. Synthesis results (using WLAN) confirm a significant reduction in energy (up to 36%), power (up to 28%), and configuration memory requirements (up to 36%), compared to state of the art.
Starting Page	104
Ending Page	112
File Size	790367
Page Count	9
File Format	PDF
ISBN	9781479901036
DOI	10.1109/SAMOS.2013.6621112
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-15
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Greedy algorithms Wireless LAN Runtime Computer architecture Parallel processing Resource management Radio spectrum management
Content Type	Text
Resource Type	Article

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