NDLI: An embedded hardware-efficient architecture for real-time cascade Support Vector Machine classification

Content Provider	IEEE Xplore Digital Library
Author	Kyrkou, C. Theocharides, T. Bouganis, C.-S.
Copyright Year	2013
Description	Author affiliation: Electr. & Electron. Eng. Dept., Imperial Coll. London, London, UK (Bouganis, C.-S.) \|\| Dept. of Electr. & Comput. Eng., Univ. of Cyprus, Nicosia, Cyprus (Kyrkou, C.; Theocharides, T.)
Abstract	Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, especially when considering embedded applications. Cascade SVMs have been proposed in an attempt to speed-up classification times, but improved performance comes at a cost of additional hardware resources. Consequently, in this paper we propose an optimized architecture for cascaded SVM processing, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings for embedded applications. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources and a 20% reduction in power, with only 0.7% reduction in classification accuracy.
Starting Page	129
Ending Page	136
File Size	1421903
Page Count	8
File Format	PDF
ISBN	9781479901036
DOI	10.1109/SAMOS.2013.6621115
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-07-15
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real-time and Embedded Systems Support vector machine classification Cascade Classifier Computer architecture Parallel processing Hardware Vectors Field Programmable Gate Arrays Kernel Support Vector Machines Parallel Architecture
Content Type	Text
Resource Type	Article

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