NDLI: Design of Operational Amplifier with Low Power Consumption in 0.35 μm Technology

Content Provider	IEEE Xplore Digital Library
Author	Kolczynski, J.
Copyright Year	2007
Description	Author affiliation: Tech. Univ. of Lodz, Lodz (Kolczynski, J.)
Abstract	This article covers the topic of designing the operational amplifiers, it describes the design of a compact, low power amplifier utilizing 0.35 μm CMOS technology. The main motivation behind this work was the existing need at the Technical University of Lodz for compact device that could be easily employed in larger designs. This article describes best topology for each stage in terms of meeting the design goals. The final circuit is a unique combination of low power topologies with solutions from large gain, high power amplifiers. This was done to achieve largest possible value of amplifier's gain within total power consumption constraint. The device performance was verified positively both at the schematic and at the layout level.
Starting Page	266
Ending Page	269
File Size	446362
Page Count	4
File Format	PDF
ISBN	8392263243
DOI	10.1109/MIXDES.2007.4286164
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-21
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz Dept of Microelectronics & Computer Science
Subject Keyword	Operational amplifiers Energy consumption Operational amplifier Design methodology MOSFETs Circuit topology Low voltage CMOS Rail to rail inputs Power consumption CMOS technology Differential amplifiers Transconductance
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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