NDLI: Tradeoffs and Optimization in Analog CMOS Design

Content Provider	IEEE Xplore Digital Library
Author	Binkley, D.M.
Copyright Year	2007
Description	Author affiliation: Univ. of North Carolina at Charlotte, Charlotte (Binkley, D.M.)
Abstract	The selection of drain current, inversion coefficient, and channel length for each MOS device in an analog circuit results in significant tradeoffs in performance. The selection of inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This paper gives hand expressions motivated by the EKV MOS model and measured data for MOS device performance, inclusive of velocity saturation and other small-geometry effects. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18-mum CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area.
Starting Page	47
Ending Page	60
File Size	945017
Page Count	14
File Format	PDF
ISBN	8392263243
DOI	10.1109/MIXDES.2007.4286119
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-21
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz Dept of Microelectronics & Computer Science
Subject Keyword	Circuit optimization Area measurement Distortion Optimization Design optimization Semiconductor device modeling Transconductance efficiency Voltage Bandwidth Analog CMOS Velocity measurement Flicker noise Transconductance moderate strong inversion Operational amplifiers Early voltage Analog circuits MOS design Inversion coefficient EKV MOS model MOS devices Weak Tradeoffs Operational transconductance amplifier Thermal noise Sizing Mismatch Channel length Gain
Content Type	Text
Resource Type	Article

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