NDLI: NNEP, Design Pattern for Neural-Network-Based Embedded Systems

Content Provider	IEEE Xplore Digital Library
Author	Esmaeilzadeh, H. Jamali, M.R. Saeedi, P. Moghimi, A. Lucas, C. Fakhraie, S.M.
Copyright Year	2007
Description	Author affiliation: Univ. of Tehran, Tehran (Esmaeilzadeh, H.; Jamali, M.R.; Saeedi, P.; Moghimi, A.; Lucas, C.; Fakhraie, S.M.)
Abstract	With time-to-market getting the most important issue in system design, reusing the design experiences as well as the IP cores is becoming very critical. Design patterns, intended for simplifying the reuse process, are design experiences that worked well in the past and documented to be reused in the future. In this paper, a design pattern named NnEP (Neural-network-based Embedded systems design Pattern) is introduced for employing neural networks, common bio-inspired solutions, in SoC-based embedded systems. This pattern is based on NnSP IP suite, a stream processing core and its tool chain, NnSP Builder and Stream Compiler. NnEP is introduced for enhancing and automating reuse in design of intelligent SoC's requiring high-speed parallel computations specially those based on neural networks. The NnEP pattern consists of the semi-automated steps, extracted from design experiences, a designer takes using the provided software suite to realize a NN application in an intelligent SoC. This includes the application analysis and pre-processing procedure, building the best-match IP core with the application, and finally compiling the intended NN application on the target IP core. On the other hand, ASIC 0.18 mum implementation results of NnSP soft core show that the core can achieve the speed of 51.2 GOPS, 25.6 GMAC/s. This throughput is comparable with the existing parallel solutions and higher in an order of magnitude from common general-purpose-processor-based solutions. This high throughput in conjunction with the inherent reusable architecture of NnSP, makes NnEP a powerful design pattern for cutting-edge neural-network-based embedded applications such as pattern recognition which is elaborated as a case study in the proposed design pattern.
Starting Page	673
Ending Page	678
File Size	347164
Page Count	6
File Format	PDF
ISBN	8392263243
DOI	10.1109/MIXDES.2007.4286248
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-21
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Tech Univ of Lodz Dept of Microelectronics & Computer Science
Subject Keyword	Process design Buildings Time to market SoC implementation Throughput Stream processors Application software Concurrent computing Intelligent networks Embedded systems Embedded system Neural networks Computer networks
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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