NDLI: A digitally assisted 20MHz–600MHz 16-phase DLL enhanced with dynamic gain control loop

Content Provider	IEEE Xplore Digital Library
Author	Hejazi, A. Kazeminia, S. Abdollahi, R.
Copyright Year	2015
Description	Author affiliation: Dept. of Microelectron. Eng., Urumi Grad. Inst., Urmia, Iran (Hejazi, A.) \|\| Dept. of Electr. Eng., Urmia Univ. of Technol., Urmia, Iran (Kazeminia, S.) \|\| Microelectron. Res. Lab., Urmia Univ., Urmia, Iran (Abdollahi, R.)
Abstract	In the proposed low-jitter delay locked loop (DLL), the analog charge pump (CP) is replaced by combination of binary accumulator (ACC) and digital-to-analog converter (DAC) to solve the problem of achieving small loop gains and mirroring small currents. Also, the problem of leakage currents during the lock state is removed when DAC provides a fixed analog voltage based on the ACC's output digital code. A simple lock detector is utilized to deactivate ACC and to generate a fixed control voltage for delay elements when the loop locks. Another loop is also applied to dynamically control loop-gain and lock time. Loop-Gain decreases (increases) when DLL moves toward (away from) the lock condition to not only guarantee the loop stability but, provide a fast lock time. Smaller jitter is expected on the generated phases comparing to the analog CPs. Here, a fixed control voltage is provided by DAC and the leakage currents cannot affect the control voltage. RMS jitter of less than 33.5ps and 1.6ps are achieved at 20MHz and 625MHz operating frequencies, respectively. Lock time is reduced from 38μs to 2μs at 20MHz and also from 900ns to 45ns at 600MHz where loop-gain is multiplied by 16, 8 and 4 for out of lock region. Total power consumption is 7.85mW at 1.8V supply voltage in a 0.18μm CMOS process.
Starting Page	1
Ending Page	4
File Size	2473685
Page Count	4
File Format	PDF
e-ISBN	9781479998777
DOI	10.1109/ECCTD.2015.7300073
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-24
Publisher Place	Norway
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delay Locked Loops Wide-Range DLL Detectors Dynamic Lock Control Jitter Delays Leakage currents Low-Jitter Clock Generation Voltage control Adders Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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