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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Martinez-Rodriguez, M.C. Baturone, I. Brox, P. |
| Copyright Year | 2011 |
| Description | Author affiliation: Microelectronics Institute of Seville (IMSE-CNM), Spanish National Research Council (CSIC), Spain (Brox, P.) || Department of Electronics and Electromagnetism, University of Seville, Spain (Martinez-Rodriguez, M.C.; Baturone, I.) |
| Abstract | This paper introduces a digital architecture to implement piecewise-affine (PWA) functions based on representation methods from the lattice theory. Given an explicit and continuous PWA function, the parameters required to implement the lattice approach can be obtained by an off-line preprocessing that can be automated. Other advantages of the proposal are that it implements a continuous PWA function with potentially no errors and the minimum number of parameters to store. This has been proven experimentally by implementing the proposal in a Xilinx FPGA and comparing its performance with other implementations, all of them addressing a typical non linear control problem. |
| Starting Page | 644 |
| Ending Page | 647 |
| File Size | 269145 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457706172 |
| e-ISBN | 9781457706189 |
| e-ISBN | 9781457706165 |
| DOI | 10.1109/ECCTD.2011.6043625 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-29 |
| Publisher Place | Sweden |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Lattices Binary search trees Throughput Proposals Integrated circuit modeling Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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