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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Grzechca, D. |
| Copyright Year | 2011 |
| Description | Author affiliation: Institute of Electronics, Silesian University of Technology, Gliwice, Poland (Grzechca, D.) |
| Abstract | The paper presents new hybrid procedure for analog circuit fault clustering with the use of simulated annealing and self-organizing neural network. Main goal of the method is to find best PWL excitation under maximum diagnosability of the circuit. Optimization is done with simulated annealing. For each node in the optimization the goal function ranks how well a neural network performs in the classification of the circuit of interest. The testing procedure is performed in time domain and therefore simulated annealing optimizes piece wise linear (PWL) excitation. The neural network input data comes from the circuit test point(s). Self-organizing map (SOM) has been applied in order to cluster all circuit states into possible separate groups. So, it works as a feature selector and classifier. The procedure has been applied for ECG amplifier and then results have been evaluated. The hybrid approach shows good efficiency in reasonable time. |
| Starting Page | 49 |
| Ending Page | 52 |
| File Size | 279251 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457706172 |
| e-ISBN | 9781457706189 |
| e-ISBN | 9781457706165 |
| DOI | 10.1109/ECCTD.2011.6043396 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-29 |
| Publisher Place | Sweden |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | self organizing map Correlation simulated annealing Simulated annealing Silicon Circuit faults analog fault diagnosis neural network Indium phosphide Testing ECG amplifier |
| Content Type | Text |
| Resource Type | Article |
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