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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Unutulmaz, A. Dundar, G. Fernandez, F.V. |
| Copyright Year | 2011 |
| Description | Author affiliation: School of Electrical and Electronics Engineering, Bogazici University, Turkey (Unutulmaz, A.; Dundar, G.) || Institute of Microelectronics of Sevilla, CSIC and University of Sevilla, Spain (Fernandez, F.V.) |
| Abstract | Automatic synthesis of analog circuits is being extensively studied and layout parasitics are increasingly being considered in the design loop. Layouts are built either through optimization or by instancing a template. In a circuit synthesis loop, the first approach is very expensive in terms of time complexity and the second one may lead low quality layouts. A better methodology will be to combine these approaches. However, a new type of router is required for such a combination; namely, the template router. This paper presents a template router and discusses how routing is coded and how this code is generated using the well known A* Algorithm. |
| Starting Page | 334 |
| Ending Page | 337 |
| File Size | 4980321 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457706172 |
| e-ISBN | 9781457706189 |
| e-ISBN | 9781457706165 |
| DOI | 10.1109/ECCTD.2011.6043354 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-29 |
| Publisher Place | Sweden |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Layout Analog circuits Routing Educational institutions Circuit synthesis Electronic mail Optimization |
| Content Type | Text |
| Resource Type | Article |
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