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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Altermann, J. Costa, E. Almeida, S. |
| Copyright Year | 2011 |
| Description | Author affiliation: Laboratory of Microelectronics and Signal Processing, Catholic University of Pelotas - UCPel, Brazil (Altermann, J.; Costa, E.; Almeida, S.) |
| Abstract | This paper proposes high performance dedicated hardware architecture for the Haar Wavelet transform, whose structure is based on nine levels of decomposition. The architecture is described in hardware description language VHDL, and it has been designed by using fixed point arithmetic, and also using efficient arithmetic operators into their sub modules. The efficiency of the architecture was proved by showing that the error from both the signals of the architecture and the signals from a reference model, described in float point in the $MATLAB^{®}$ environment, is negligible. Moreover, the synthesis results clearly show the higher performance of the proposed architecture over other solutions from the literature, where gains in terms of frequency operation and area utilization are reported. |
| Starting Page | 596 |
| Ending Page | 599 |
| File Size | 344176 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781457706172 |
| e-ISBN | 9781457706189 |
| e-ISBN | 9781457706165 |
| DOI | 10.1109/ECCTD.2011.6043604 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-29 |
| Publisher Place | Sweden |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Architectural Exploration Computer architecture Haar Wavelet Transform Filter Banks Logic Synthesis Discrete wavelet transforms Mathematical model Delay Clocks |
| Content Type | Text |
| Resource Type | Article |
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