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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Saiyu Ren Siferd, R. |
| Copyright Year | 2011 |
| Abstract | A CMOS ADC architecture is presented that combines pipelined low pass ADCs with time interleaving to obtain sampling frequencies in the 3 to 6 GHz range with bandwidths of 1.5 to 3 GHz and 10-12 bits of resolution. The schematic design and performance simulations are included for a 180 nm CMOS process. The Time Interleaved Pipelined (TIP) ADC samples at 3.2 GHz with inputs in either the first or second Nyquist region and has 12 bits resolution while consuming 900 mW of power with 1.8 v power supply. |
| Starting Page | 785 |
| Ending Page | 790 |
| File Size | 368010 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612844275 |
| DOI | 10.1109/ITNG.2011.137 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-04-11 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Bandwidth circular buffer Time frequency analysis Generators time interleaving CMOS integrated circuits Frequency division multiplexing wide bandwidth CMOS low pass ADC Delay Clocks high resolution |
| Content Type | Text |
| Resource Type | Article |
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