NDLI: Hybrid-way Cache for Mobile Processors

Content Provider	IEEE Xplore Digital Library
Author	Deepika, B.L. Byeong Kil Lee
Copyright Year	2011
Abstract	As multi-core trends are becoming dominant, cache structures are being sophisticated and complicated. Also, the bigger shared level-2 (L2) caches are demanded for higher cache performance. However, the big cache size is directly related to the area and power consumption. Designing a cache memory, one of the easiest ways to increase the performance is doubling the cache size. In mobile processors, however, simple increase of the cache size may significantly affect its chip area and power. To address this issue, in this paper, we propose the hy-way cache (hybrid-way cache) which is a composite cache mechanism to maximize cache performance within a given cache size. This mechanism can improve cache performance without increasing cache size and set associativity by emphasizing the utilization of primary way(s) and pseudo-associativity. Based on our experiments with the sampled SPEC CPU2000 workload, the proposed cache mechanism shows the remarkable reduction in cache misses with the penalty of additional hardware cost and additional power consumption. The variation of performance improvement depends on cache size and set associativity, but the proposed scheme shows more sensitivity to cache size increase than set associativity increase.
Starting Page	707
Ending Page	712
File Size	378282
Page Count	6
File Format	PDF
ISBN	9781612844275
DOI	10.1109/ITNG.2011.125
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-04-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation set associative cache Program processors Power demand Benchmark testing Mobile communication mobile processor Hardware cache design Arrays
Content Type	Text
Resource Type	Article

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