NDLI: Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures

Content Provider	IEEE Xplore Digital Library
Author	Rahmani, A.-M. Latif, K. Vaddina, K.R. Liljeberg, P. Plosila, J. Tenhunen, H.
Copyright Year	2011
Description	Author affiliation: Turku Centre for Computer Science (TUCS), University of Turku, Finland (Rahmani, A.-M.; Vaddina, K.R.; Plosila, J.) \|\| University of Turku, Finland (Latif, K.; Liljeberg, P.; Tenhunen, H.)
Abstract	Three-dimensional IC technology offers greater device integration and shorter interlayer interconnects. In order to take advantage of these attributes, 3D stacked mesh architecture was proposed which is a hybrid between packet-switched network and a bus. Stacked mesh is a feasible architecture which provides both performance and area benefits, while suffering from inefficient intermediate buffers. In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called Adaptive-Z for vertical communication. In addition, we hybridize the proposed adaptive routing with available algorithms to mitigate the thermal issues by herding most of the switching activities closer to the heat sink. Our extensive simulations with synthetic and real benchmarks, including the one with an integrated video-conference application, demonstrate significant power, performance, and peak temperature improvements compared to a typical stacked mesh 3D NoC.
Starting Page	65
Ending Page	72
File Size	1504114
Page Count	8
File Format	PDF
ISBN	9781450307208
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Thermal Management 3D ICs Routing Algorithm Thermal resistance Routing Three dimensional displays Silicon 3D NoC-Bus Hybrid Architecture Heat sinks Fault Tolerance
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures

A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication

Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures

Power-Efficient Inter-Layer Communication Architectures for 3D NoC

An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip

High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET-Based Adaptive Monitoring Platform

Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures

Similar Documents

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures

A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication

Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures

Power-Efficient Inter-Layer Communication Architectures for 3D NoC

An Efficient Hybridization Scheme for Stacked Mesh 3D NoC Architecture

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip

High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET-Based Adaptive Monitoring Platform

Fault-tolerant routing algorithm for 3D NoC using hamiltonian path strategy

HARS: A High-Performance Reliable Routing Scheme for 3D NoCs

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures