NDLI: Prevention flow-control for low latency torus networks-on-chip

Content Provider	IEEE Xplore Digital Library
Author	Joshi, A. Mutyam, M.
Copyright Year	2011
Description	Author affiliation: Computer Architecture and Systems Lab, Department of Computer Science & Engineering, Indian Institute of Technology, Madras, India (Joshi, A.; Mutyam, M.)
Abstract	The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and keep the simplicity of a mesh network, torus network is proposed. As torus networks have inherent circular dependency, additional effort is needed to prevent deadlock, even if deadlock free routing algorithms are used. We describe a novel flow-control mechanism to address cost/performance constraints in torus networks and ensure freedom from deadlock. Flow-control is achieved using a prevention mechanism which uses virtual cut-through switching, and deadlock freedom is achieved by considering only a single packet buffer per input port. We can simplify the router design by having a simple switch allocator, which prioritizes insight packets, and a single packet buffer per input port, which eliminates the need for virtual channels. Experimental validation reveals that our design achieves significant improvement in throughput, as compared to the traditional design, using significantly fewer buffers.
Starting Page	41
Ending Page	48
File Size	1251211
Page Count	8
File Format	PDF
ISBN	9781450307208
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Deadlock Protocols Networks-on-Chip Pipelines Torus Switches System recovery Throughput Routing Complexity theory Flow-control
Content Type	Text
Resource Type	Article

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