NDLI: Cross clock-domain TDM virtual circuits for networks on chips

Content Provider	IEEE Xplore Digital Library
Author	Zhonghai Lu
Copyright Year	2011
Description	Author affiliation: Dept. of Electronic Systems, School of ICT, KTH - Royal Institute of Technology, Sweden (Zhonghai Lu)
Abstract	We propose cross clock-domain time-division-multiplexing (TDM) Virtual Circuit (VC), in short, VC, to provide delay and bandwidth guaranteed communication for NoCs with multiple clock domains. The cross-domain VC extends the synchronous VC in a single clock domain to multiple clock domains. The synchronous VCs reserve cyclic time slots at each node from source to destination for a traffic flow to use shared links without contention based on the assumption that all nodes share the same notion of time. However, when VCs pass multiple clock domains with different phases and frequencies, the assumption of global synchrony is not valid any more and consequently they cannot function correctly. This paper addresses this problem based on a typical FIFO clock domain interface. We give the conditions and a realization scheme to ensure correct packet delivery with QoS for VCs crossing multiple clock domains. We apply network calculus to analyze and derive the bounds of the packet delay and the FIFO size.
Starting Page	209
Ending Page	216
File Size	176543
Page Count	8
File Format	PDF
ISBN	9781450307208
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Quality-of-Service (QoS) Network Calculus Bandwidth Quality of service Receivers Network-on-Chip (NoC) Synchronization Delay Clocks
Content Type	Text
Resource Type	Article

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