NDLI: FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations

Content Provider	IEEE Xplore Digital Library
Author	Papamichael, M.K. Hoe, J.C. Mutlu, O.
Copyright Year	2011
Description	Author affiliation: Electrical and Computer Engineering Department, Carnegie Mellon University, Pittsburgh, PA, USA (Hoe, J.C.; Mutlu, O.) \|\| Computer Science Department, Carnegie Mellon University, Pittsburgh, PA, USA (Papamichael, M.K.)
Abstract	FIST (Fast Interconnect Simulation Techniques) is a fast and simple packet latency estimator to replace time-consuming detailed Network-on-Chip (NoC) models in full-system performance simulators. FIST combines ideas from analytical network modeling and execution-driven simulation models. The main idea is to abstractly model each router as a load-delay curve and sum load-dependent delay at each visited router to obtain a packet's latency by tracking each router's load at runtime. The resulting latency estimator can accurately capture subtle load-dependent behaviors of a NoC but is much simpler than a full-blown execution-driven model. We study two variations of FIST in the context of a software-based, cycle-level simulation of a tiled chip-multiprocessor (CMP). We evaluate FIST's accuracy and performance relative to the CMP simulator's original execution-driven 2D-mesh NoC model. A static FIST approach (trained offine using uniform random synthetic traffic) achieves less than 6% average error in packet latency and up to 43× average speedup for a 16×16 mesh. A dynamic FIST approach that adds periodic online training reduces the average packet latency error to less than 2% and still maintains an average speedup of up to 18× for a 16×16 mesh. Moreover, an FPGA-based realization of FIST can simulate 2D-mesh networks up to 24×24 nodes, at 3 to 4 orders of magnitude speedup over software-based simulators.
Starting Page	137
Ending Page	144
File Size	736640
Page Count	8
File Format	PDF
ISBN	9781450307208
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Training Analytical models Accuracy Full-System Simulation Computational modeling Performance Models FPGA Network-on-Chip Hardware Modeling Field programmable gate arrays Load modeling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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