NDLI: Tanh-like Activation Function Implementation for High-performance Digital Neural Systems

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Table of contents

A Voltage Efficient PMOS Charge Pump Architecture

Switched capacitor non-linear function synthetizer based on a novel iterative method

A Low-Ripple Fast-Settling CMOS Envelope Detector

A 600mV Baseband Analog Filter for UMTS Receivers

A Low Voltage Low Power DCCII and MRC-based $2^{nd}Order$ Multiple-Output Filter

A Programmable Double Supply Filter&Drive Block for Telecommunication Applications

A fully integrated very low frequency single-ended Gm-C filter based on a novel transconductor

Continuous vs. Piecewise Hysterisis Model of a Current Transformer

Power Supply Generation in CMOS Passive UHF RFID Tags

An RTL-to-Grid Design Flow for Power Grid Verification Based on a Statistical Estimation Engine

Thermal Mapping of Power Devices with a Completely Automated Thermoreflectance Measurement System

Comparison of calculation techniques ofconstant VSWR impedance circle: evaluation of power transistors robustness

Analysis of the Substrate Noise Effects due to DC-DC Converter Integration

Random switching frequency in a synchronous-asynchronous digital voltage-mode control for dc-dc converters

Design, Assembly and Testing of Modular Multilevel Converter with Multicarrier PWM Method

A New Scheme to Reduce Leakage in DeepSubmicron Cache Memories with No Extra Dynamic Consumption

Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits Assignment

Profiling Charge Distribution in $NROM^{TM}Devices$

An FPGA-Based Software Defined Radio Platform for the 2.4GHz ISM Band

A Flexible FPGA/DSP Board for GNSS Receivers Design

Designing an Independent Speaker Isolated Speech Recognition System on an FPGA

Evaluation of Hierarchical FPGA partitioning methodologies based on architecture Rent Parameter

Angular Modulation of Injection Locked Oscillators

A Distributed Voltage Controlled Oscillator in a standard 65nm CMOS Process

Reduction of CMOS Inverter Ring Oscillator Close-in Phase Noise by Current Mode Instead of Voltage Mode Supply

A VCO's Phase-Noise Reduction Technique

A fully-integrated 60 GHz VCO in l3Onm SOI-CMOS on high-resistivity substrate

A Low-Power VLSI architecture for Intra and Inter prediction in H.264

An Edge Preserving Spatial Error Concealment Technique for the H.264 Video Coding Standard

Reduced Computation Mode decision using Error Domain heuristics for the H264 standard

Design Methodology for fΣΔ Modulators

An Incremental Data Converter with an Oversampling Ratio of 3

High-IF Sampling Continuous-Time Bandpass ΔΣ Modulator

Low Power, Third Order ΣΔ Modulator with Cross-Coupled Paths for WCDMA Applications

An electronically tunable voltage-mode universal filter using two current conveyors

Power-minimization Design Procedure for Rauch Biquadratic Cells

Design Techniques for VHF Filtering in Digital CMOS Technologies

Design and Comparison of CMOS CCII Based Shapers for Detector Readout Front Ends

Reversed Double Pole-Zero Cancellation Frequency Compensation Technique for Three-Stage Amplifiers

Development of a Design Platform for CMOS Amplifiers

Common Source Amplifier with Feedback Biasing in 9Onm CMOS

A Low-Power adaptive biasing CMOS Operational Amplifier with enhanced DC-Gain

A single-ended-to-differential transimpedence amplifier for a voice transceiver analog interface

Programmable OTA Based CMOS Shaping Amplifier for X-rays Spectroscopy

Elimination of Switch On-State Resistance Effect on a Switched-Capacitor Filter Characteristic

1.5GHz fully differential latched current comparator with 20nA of sensitivity

An Analogue CMOS Neural Circuit for Improved Sensing

Automatic Wavelet Localization and Adaptive Meshing of Physical Relevances in Device Simulation

A Novel Methodology for Defining the Boundaries of Geometrical Discontinuities in Electronic Packages

Towards Very High Frequency Simulators for Active Device Modelling

VCSELs modeling and simulation

An Integrated Flow from pre-Silicon Simulation to post-Silicon Verification

A fully-automatic CAD toolbox for a MOS drain current model and its parameters extraction

LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions

A New Paradigm and Associated Tools for TLM/T Modeling of MPSoCs

Router IP macrocell for radiation tolerant SpaceWire Networking

An Error-Correcting Line Encoding ASIC for a HEP Rad-Hard Multi-GigaBit Optical Link

A VHDL model and Implementation of a Coarse-Grain Reconfigurable Coprocessor for a RISC Core

Power-Delay Optimized Design of Cascaded ECL Gates

Tanh-like Activation Function Implementation for High-performance Digital Neural Systems

Programmable Switch for Shared Bus Replacement

Reduced complexity Eye Detector for colour images using Harris Corners, Color heuristics and Edge maps

Selection of Initial Quantisation Parameter for Rate Controlled 1.264 video coding

Cellular Neural Networks for Object-oriented Segmentation

A reconfigurable CMOS iinager for real-time, spatio-ternporal image processing with on-chip ADC

3DJAM: A Linear CMOS Sensor for 3D Vision with Merged I-TOF and OT Techniques

Alternative color filter array layouts for digital photography

A 120dB CMOS Imager with a Light Adaptive System and Digital Outputs

Sensitivity analysis of a passive inductive telemetry system for a capacitive sensor

Using an Electric Programmable Analog Array for IEEE 1451 compliant Transducer Applications

VLSI Electronics Design and Testing for the Silicon Drift Sensor System of the ALICE Experiment

Design of a 1.8V 6bits Low Power F/I CMOS A/D Converter with a Novel Folder-Reduction Technique

DAC nonlinearity and residue gain error correction in a pipelined ADC using a split-ADC architecture

A Very Low-Power CMOS 11-b Cyclic A/D Converter with Mismatch Compensation

Efficient Calibration through Statistical Behavioral Modeling of a High-Speed Low-Power ADC

A 6-bit, 1.2 GHz Interleaved SAR ADC in 90nm CMOS

ESD Protection Design for CMOS Integrated Circuits with Mixed-Voltage I/O Interfaces

Mathematical Analysis of Digital MASH Delta-Sigma Modulators for Fractional-N Frequency Synthesizers

Efficient Polynomial Inversion for the Linearization of Pipeline ADCs

The O-Sequence: Representation of 3D-Floorplan Dissected by Rectangular Walls

Hierarchical Graph-Based Sizing for Analog Cells Through Reference Transistors

A generic modeling approach for molecule-gated nanowire transistors using VHDL-AMS

A Model to Understand Current Consumption, Maximum Operating Frequency and Scaling Trends of MCML Frequency Dividers

Design of FPGA-based Hardware Accelerators for On-line Fingerprint Matcher Systems

A TLM Design for Verification Methodology

Quantized Conductance: an overview from the electronic engineering side

HDL Library of Processing Units for an Automatic LDPC Decoder Design

Simultaneous multi-standard support in programmable baseband processors

RNS-based Watermarking for IP Cores

Using Multiple-Valued Gates to Implement Reversible Logic

Synchronous to Asynchronous Conversion of Digital Circuits

How to Add the Integrity Checking Capability to Block Encryption Algorithms

Design, testing and prototyping of a software programmable I2C/SPI IP on AMBA bus

A Low Power 128-pt Implementation of FFT/IFFT for High Performance Wireless Personal Area Networks

Pile Up Rejection and Multiple Simultaneous Events Acquisition with the PDD ASIC

A Switched Capacitor Interface for a Capacitive Microphone

ASIC for fast and high resolution position measurement

Fast Prototyping Flow for Sensor Interfaces

Fabrication of low-threshold 1.3-μm InAs/InGaAs/GaAs quantum-dot lasers operating at room temperature

Parallel Chains based Read-out System for a Compton Enhanced 3D PET Scanner

Synergies of Controller-Based LED Drivers and Quality Solid-State Lighting

Multilayer PCB Planar Fluxgate Magnetic Sensor

Hard X-Ray SOI Sensor Prototype

Integration of SAW filter on PICS substrate using polymer sealing

High-quality MOCVD AlGaN/GaN structure for HEMT applications

A 1 $cm^{3}Modular$ Autonomous Sensor Node for Physical Activity Monitoring

Carbon-monoxide (CO) Real Time Monitoring in Combustion Engines by an Optical Detection System

Bioimpedance spectroscopy for cell characterization in the 50Hz-5MHz frequency range

CMOS Low-Noise Amplifier Analysis and Optimization for Wideband Applications

A Wideband LNA for Wireless Multistandard Receiver in l30nm CMOS SOI Process

Graphical Optimization of Common-Gate LNA

A 0.25-μm CMOS Low-Power Up-Conversion Mixer for 3.1-5 GHz Ultra-Wideband Applications

A Wideband FM Demodulator for UWB Applications

UWB Receiver Design and Two-Way-Ranging Simulation using VHDL-AMS

On the Design of Ultra Wideband FCC Compliant Integrated Radars

A Frequency Plan Evaluation Tool for Multi-standard Wireless Transceivers

Linearity measurements of Si/SiGe Heterojunction Bipolar Transistor using a Large Signal Network Analyzer with an harmonic Load-Pull setup

A 24-GHz Automotive Radar Transmitter with Digital Beam Steering in 130-nm CMOS

The Effect of 1/f Noise on the Spectrum and the Jitter of a Free Running Oscillator

Impact of Scaling on CMOS Radio Frequency Class-E Power Amplifiers

T-Proc: An Embedded IEEE1500-Wrapped Cores Tester

Lightweight Time Encoded Signal Processing for Vehicle Recognition in Sensor Networks

On checking causality of bandlimited sampled frequency responses

A Unified Synchronization Algorithm for OFDM Systems in Multipath Fading Channel

Research in Microelectronics and Electronics, 2005 PhD

Tanh-like Activation Function Implementation for High-performance Digital Neural Systems

Content Provider	IEEE Xplore Digital Library
Author	Marra, S. Iachino, M.A. Morabito, F.C.
Copyright Year	2006
Description	Author affiliation: Dept. of Informatics, Math., Electron. & Transp., Reggio Calabria Univ. "Mediterranea" (Marra, S.; Iachino, M.A.; Morabito, F.C.)
Abstract	In this paper, a high-performance implementation of a programmable tanh-like activation function is presented. The proposed function can be successfully used to train neural networks obtaining generalization ability slightly better than standard activation functions. The achieved accuracy, the high computational speed and the small amount of area resources make the proposed solution ideal for digital implementations
Starting Page	237
Ending Page	240
File Size	4137829
Page Count	4
File Format	PDF
ISBN	1424401577
DOI	10.1109/RME.2006.1689940
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-12
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Neurons Neural networks Integrated circuit interconnections Artificial neural networks Hardware Computer networks Informatics Field programmable gate arrays Arithmetic
Content Type	Text
Resource Type	Article

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