NDLI: Early experiments on the CAM-Brain Machine (CBM)

Content Provider	IEEE Xplore Digital Library
Author	de Garis, H. de Penning, L. Buller, A. Decesare, D.
Copyright Year	2001
Description	Author affiliation: Brain Builder Group, STARLAB, Brussels, Belgium (de Garis, H.)
Abstract	This paper presents results of some of the first evolution experiments undertaken on an actual CAM-Brain Machine (CBM), using the hardware itself and not software simulations. A CBM is a specialised piece of programmable (evolvable) hardware that uses Xilinx XC6264 programmable FPGA chips to grow and evolve, at electronic speeds, 3D cellular automata (CA) based neural network circuit modules of some 1000 neurons each. A complete run of a genetic algorithm (e.g. with 100 generations and a population size of 100) is executed in a few seconds. 64000 of these modules can be evolved separately according to the fitness definitions of human "EEs" (evolutionary engineers) and downloaded one by one into a gigabyte of RAM. Human "BAs" (brain architects) then interconnect these modules "by hand" according to their artificial brain architectures. The CBM then updates the binary neural signaling of the artificial brain (with 64000 "hand" interconnected modules, i.e. 75 million neurons) at a rate of 130 billion CA cell updates a second, which is fast enough for real time control of robots. Before such multi-moduled artificial brains can be constructed. It is essential that the quality of the evolution (the "evolvability") of individual modules be adequate. This paper reports on the first evolution results obtained on CBM hardware.
Sponsorship	NASA
Starting Page	211
Ending Page	219
File Size	840913
Page Count	9
File Format	PDF
ISBN	0769511805
DOI	10.1109/EH.2001.937964
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-07-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neurons Humans Integrated circuit interconnections Circuit simulation Neural network hardware Field programmable gate arrays Biological neural networks Cellular neural networks Neural networks Genetic algorithms
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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