NDLI: ESD Protection Design for CMOS Integrated Circuits with Mixed-Voltage I/O Interfaces

Content Provider	IEEE Xplore Digital Library
Author	Wei-Jen Chang Ming-Dou Ker
Copyright Year	2006
Description	Author affiliation: Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu (Wei-Jen Chang; Ming-Dou Ker)
Abstract	With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-mum CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces
Starting Page	305
Ending Page	308
File Size	398759
Page Count	4
File Format	PDF
ISBN	1424401577
DOI	10.1109/RME.2006.1689957
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-12
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Variable structure systems Power supplies Electrostatic discharge Voltage CMOS integrated circuits Clamps Protection Diodes Stress MOS devices
Content Type	Text
Resource Type	Article

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