NDLI: A Low-Power VLSI architecture for Intra and Inter prediction in H.264

Content Provider	IEEE Xplore Digital Library
Author	Koziri, M.G. Stamoulis, G.I. Katsvounidis, I.X.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. & Commun. Eng., Thessaly Univ. (Koziri, M.G.; Stamoulis, G.I.)
Abstract	The H.264 video coding standard can achieve considerably higher coding efficiency than previous standards. The keys to this high code efficiency are mainly the two prediction modes (intra & inter) provided by the standard. Unfortunately these come at a cost in considerable increased complexity at the encoder. Therefore it is of high importance to design architectures that minimize the cost of the prediction modes. One computational element that is met in both, inter and intra prediction modes, is that of the sum of absolute differences (SAD). In this paper we present a new algorithm that can replace SAD in the two main prediction modes, and which can provide a more efficient hardware implementation
Starting Page	109
Ending Page	112
File Size	3931746
Page Count	4
File Format	PDF
ISBN	1424401577
DOI	10.1109/RME.2006.1689908
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-06-12
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Video coding Costs ISO standards Computer architecture Very large scale integration Video compression Encoding Hardware Code standards Communication standards
Content Type	Text
Resource Type	Article

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A Low-Power VLSI architecture for Intra and Inter prediction in H.264