NDLI: A time interleaved DAC sharing SAR Pipeline ADC for ultra-low power camera front ends

Content Provider	IEEE Xplore Digital Library
Author	Amaravati, A. Chugh, M. Raychowdhury, A.
Copyright Year	2015
Description	Author affiliation: Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA (Amaravati, A.; Chugh, M.; Raychowdhury, A.)
Abstract	The growing need for ultra-low power cameras for sensors, surveillance and consumer applications has resulted in significant advances in compressed domain data acquisition from pixel arrays. In this paper we present a novel 64-input Successive Approximation (SAR) Pipeline analog-to-digital converter (ADC) suitable for compressed domain data acquisition in camera front-ends. The proposed architecture features a time interleaved capacitive digital-to-analog converter (DAC) shared between column parallel ADCs for area savings (2.28X); and a shared amplifier stage for power savings (60%). Simulations on a 130nm foundry process shows that the proposed SAR Pipeline ADC draws 31μW at 2MS/s having a target Figure-of-Merit (FOM) of 87fJ/conv. per step at Nyquist rate.
Starting Page	231
Ending Page	236
File Size	1644741
Page Count	6
File Format	PDF
ISSN	23248440
e-ISBN	9781467391405
DOI	10.1109/VLSI-SoC.2015.7314421
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-05
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Compressive sensing Capacitors Pipelines Data acquisition Redundancy SAR Pipeline DAC sharing Cameras Capacitance Compressed sensing
Content Type	Text
Resource Type	Article

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