NDLI: Architecture exploration of 3D FPGA to minimize internal layer connection

Content Provider	IEEE Xplore Digital Library
Author	Amagasaki, M. Takeuchi, Y. Qian Zhao Iida, M. Kuga, M. Sueyoshi, T.
Copyright Year	2015
Description	Author affiliation: Grad. Sch. of Sci. & Technol., Kumamoto Univ., Kumamoto, Japan (Amagasaki, M.; Takeuchi, Y.; Qian Zhao; Iida, M.; Kuga, M.; Sueyoshi, T.)
Abstract	A three-dimensional (3D) integration based on wafer-to-wafer bonding using through-silicon vias (TSVs) has been developed for the fabrication of new 3D large-scale integrated chips. To balance between cost and performance, and to explore 3D field-programmable gate array (FPGA) with realistic 3D integration processes, we propose spatially distributed and functionally distributed types of 3D FPGA architectures. The functionally distributed architecture consists of two wafers, a logic layer and a routing layer, and is stacked by a face-down process technology. Since vertical wires pass through microbumps, no TSVs are needed. In contrast, the spatially distributed architecture is divided into multiple layers with the same structure, unlike in the functionally distributed type. This architecture can be expanded to more than two layers by stacking multiples of the same die. The goal of this paper is to elucidate the advantages and disadvantages of these two types of 3D FPGAs. According to our evaluation, when only two layers are used, the functionally distributed architecture is more effective. When higher performance is achieved by using more than two layers, the spatially distributed architecture achieves better performance.
Starting Page	110
Ending Page	115
File Size	1000847
Page Count	6
File Format	PDF
ISSN	23248440
e-ISBN	9781467391405
DOI	10.1109/VLSI-SoC.2015.7314401
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-05
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Three-dimensional displays Stacking Computer architecture Routing Delays Through-silicon vias Field programmable gate arrays
Content Type	Text
Resource Type	Article

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