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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Panella, A. Santambrogio, M.D. Redaelli, F. Cancare, F. Sciuto, D. |
| Copyright Year | 2010 |
| Description | Author affiliation: Dipartimento di Elettronica e Informazione (DEI) - Politecnico di Milano, Italy (Santambrogio, M.D.; Redaelli, F.; Cancare, F.; Sciuto, D.) || Computer Science Department - University of Illinois at Chicago, USA (Panella, A.) |
| Abstract | Multi-FPGA systems (MFS's) represent a promising technology for various applications, such as the implementation of supercomputers and parallel and computational intensive emulation systems. On the other hand, dynamic reconfigurability expands the possibilities of traditional FPGAs by providing them the capability of adapting their functionality while still running to cope with runtime environment changes. These two research directions are merged together in this work, that describes a methodology for designing dynamic reconfigurable MFS's. In this paper a novel MFS design flow has been described, which makes use of blocks reuse through dynamic reconfigurability to make the implementation of large systems feasible even on multi-FPGA architectures with strict physical constraints. Functional to this goal is the development of an algorithm for the extraction of the isomorphic structures of a circuit that extensively exploits the hierarchy of the design. |
| Starting Page | 414 |
| Ending Page | 419 |
| File Size | 439518 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424464692 |
| e-ISBN | 9781424464715 |
| DOI | 10.1109/VLSISOC.2010.5642697 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-09-27 |
| Publisher Place | Spain |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Layout Clustering algorithms Integrated circuit interconnections Computer architecture Partitioning algorithms Field programmable gate arrays |
| Content Type | Text |
| Resource Type | Article |
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