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2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC)

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip

2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip

Towards reverse engineering the brain: Modeling abstractions and simulation frameworks

Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study

A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications

TM-FAR: Turn-Model based Fully Adaptive Routing for Networks on Chip

A binary adaptable window SoC architecture for a stereo vision based depth field processor

Network interface to synchronize multiple packets on NoC-based Systems-on-Chip

Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip

Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper

SoCGuard: A runtime verification solution for the functional correctness of SoCs

Enhancing post-silicon processor debug with Incremental Cache state Dumping

Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis

Power-aware FPGA routing fabrics and design tools

Fine-grained post placement voltage assignment considering level shifter overhead

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs

Reduction of process variation effect on FPGAs using multiple configurations

An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks

Synchronous duty cycle correction circuit

An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector

Spatial EM jamming: A countermeasure against EM Analysis?

Ultra low voltage and high speed CMOS flip-flop using floating-gates

Static ultra-low-voltage high-speed CMOS logic and latches

An improved RNS generator $2^{n}$ ± k based on threshold logic

Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems

Optimal scheduling to minimize non-volatile memory access time with hardware cache

A reconfigurable MPSoC-based QAM modulation architecture

Design and implementation of MPSoC single chip with butterfly network

Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs

An automatic framework for dynamic data structures optimization in C

Adaptive logical control of RF LNA performances for efficient energy consumption

A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control

A high-speed high-resolution low-phase noise oscillator using self-timed rings

A highly linear wide dynamic range detector for cell recording with microelectrode arrays

A $1mm^{2}$ 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS

Area- and throughput-optimized VLSI architecture of sphere decoding

Fast fixed-point optimization of DSP algorithms

Novel input coding technique for high-precision LUT-based multiplication for DSP applications

An adaptive bilateral motion estimation algorithm and its hardware architecture

A decimal squarer with efficient partial product generation

Low complexity montgomery multiplication architecture for elliptic curve cryptography over $GF(p^{m})$

Novel ultra low-voltage and high speed domino CMOS logic

High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations

Timing and interface communication analysis of H.264/AVC encoder using SystemC model

Control electronics integration toward endoscopic capsule robot performing legged locomotion and illumination

Smart camera SoC system for interactive real-time real-brush based digital painting systems

A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS

Supporting circuitry for a fully integrated micro electro mechanical (MEMS) oscillator in 45 nm CMOS technology

Energy aware multimodal embedded video surveillance

Towards sustainable exascale computing

Trends and techniques for energy efficient architectures

Logic synthesis and testability of D-reducible functions

On the synthesis of attack tolerant cryptographic hardware

Design of low-complexity and high-speed digital Finite Impulse Response filters

A broad strategy to detect crosstalk faults in network-on-chip interconnects

A low-power, high-speed DCT architecture for image compression: Principle and implementation

Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressors

Hardware integrated quantization solution for improvement of computational H.264 encoder module

Architectural synthesis of DSP circuits under simultaneous error and time constraints

Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation

VCTA: A Via-Configurable Transistor Array regular fabric

SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications

Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits

Temperature- and bus traffic- aware data placement in 3D-stacked cache

Power-aware partitioning of data converters

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR

Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization

Characterization of chip-to-chip wireless interconnections based on capacitive coupling

A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole

A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4

A 36-mW continuous-time sigma-delta modulator with 74db dynamic range and 10-MHz bandwidth

Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations

A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC

Unifying stream based and reconfigurable computing to design application accelerators

A design workflow for dynamically reconfigurable multi-FPGA systems

Fine-grained adaptive CMP cache sharing through access history exploitation

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

2007 IFIP International Conference on Very Large Scale Integration

2006 IFIP International Conference on Very Large Scale Integration

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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