NDLI: Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Berman, A. Ginosar, R. Keidar, I.
Copyright Year	2010
Description	Author affiliation: Department of Electrical Engineering, Technion - Israel Institute of Technology, Technion City, Haifa 32000, Israel (Berman, A.; Ginosar, R.; Keidar, I.)
Abstract	Network-on-Chip (NoC) links consume a significant fraction of the total NoC power. We present Selective Packet Interleaving (SPI), a flit transmission scheme that reduces power consumption in NoC links. SPI decreases the number of bit transitions in the links by exploiting the multiplicity of virtual channels in a NoC router. SPI multiplexes flits to the router's output link so as to minimize the number of bit transitions from the previously transmitted flit. Analysis and simulations demonstrate a reduction of up to 55% in the number of bit transitions and up to 40% savings in power consumed on the link. SPI benefits grow with the number of virtual channels. SPI works better for links with a small number of bits in parallel. While SPI compares favorably against bus inversion, combining both schemes helps to further reduce bit transitions.
Starting Page	37
Ending Page	42
File Size	197999
Page Count	6
File Format	PDF
ISBN	9781424464692
e-ISBN	9781424464715
DOI	10.1109/VLSISOC.2010.5642624
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	routing Power demand network-on-chip Simulation Conferences VLSI interconnects Benchmark testing Bismuth Very large scale integration Encoding low-power design techniques
Content Type	Text
Resource Type	Article

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