NDLI: A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Battezzati, N. Sterpone, L. Violante, M. Decuzzi, F.
Copyright Year	2010
Description	Author affiliation: ESA/ESTEC, Noordwijk, The Netherlands (Decuzzi, F.) \|\| Politecnico di Torino, Italy (Battezzati, N.; Sterpone, L.; Violante, M.)
Abstract	The higher resiliency of Flash-based FPGAs to Single Event Upsets (SEUs) with respect to other non radiation-hardened devices, such as SRAM-based FPGAs, are increasing more and more their demand for avionic and space applications, where a harsh environment rich in ionizing radiation has to be faced. In this type of devices other transient faults tend to dominate over SEUs, especially when the device operates at high frequency. In this scenario, it is expected that Single Event Transient (SET) faults will predominate. As a result, designers will still need prediction techniques to forecast the effects of ionizing radiation in their designs. Although radiation testing is a feasible method for evaluating circuit sensitiveness against SETs, it is hard to implement, very expensive, and it can be used only in later phases of the design process, when a prototype of the system is available. On the other hand, simulation techniques need a first technology characterization step and also require a very detailed model for being effective; moreover they are application dependent. In this paper we propose a new software tool for analyzing designs implemented in Flash-based FPGAs and estimating SET sensitiveness. The evaluation process is static, as it does not entail any simulation. In particular, it provides worst-case results, thus being intrinsically more conservative than other dynamic methods. Experimental results are presented comparing the ones coming from radiation testing and the results provided by the presented tool. They validate the proposed approach.
Starting Page	79
Ending Page	84
File Size	291163
Page Count	6
File Format	PDF
ISBN	9781424464692
e-ISBN	9781424464715
DOI	10.1109/VLSISOC.2010.5642619
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tiles Routing Circuit faults Integrated circuit modeling Transient analysis Field programmable gate arrays Testing
Content Type	Text
Resource Type	Article

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