NDLI: A binary adaptable window SoC architecture for a stereo vision based depth field processor

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2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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A binary adaptable window SoC architecture for a stereo vision based depth field processor

Content Provider	IEEE Xplore Digital Library
Author	Motten, A. Claesen, L.
Copyright Year	2010
Description	Author affiliation: Expertise Centre for Digital Media, Hasselt University - tUL - IBBT, Wetenschapspark 2, 3590 Diepenbeek, Belgium (Motten, A.; Claesen, L.)
Abstract	This paper presents a novel binary fully adaptable window for incorporating in a stereo matching System-on-Chip (SoC) architecture. This architecture is fully scalable and parameterizable to allow for custom SoC implementations, as well as rapid prototyping on FPGAs. For each window a binary mask window is generated which selects the supporting pixels in the cost aggregation phase of the SAD algorithm. This selection is performed using color similarity and spatial distance metrics. Hardware resource utilization for a fixed window and an adaptable window cost aggregation is compared based on FPGA logic element use.
Starting Page	25
Ending Page	30
File Size	462931
Page Count	6
File Format	PDF
ISBN	9781424464692
e-ISBN	9781424464715
DOI	10.1109/VLSISOC.2010.5642626
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-27
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FPGA System-on-Chip cost aggregation Registers component Image color analysis stereo matching Computer architecture adaptable window computer vision Hardware Stereo vision System-on-a-chip Pixel
Content Type	Text
Resource Type	Article

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