NDLI: Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

Content Provider	IEEE Xplore Digital Library
Author	Jun So Pak Chunghyun Ryu Jaemin Kim Yujeong Shim Gawon Kim Joungho Kim
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon (Jun So Pak; Chunghyun Ryu; Jaemin Kim; Yujeong Shim; Gawon Kim; Joungho Kim)
Abstract	In this paper, we show the advantages of 3D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 mum) and large pitch (200 mum) TSV with thick silicon substrate (Si, 80 mum, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm times 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 mum thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor radic(2).
Starting Page	351
Ending Page	354
File Size	692281
Page Count	4
File Format	PDF
ISBN	9789810806293
DOI	10.1109/APEMC.2008.4559884
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-19
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Asia Pacific EMC Society
Subject Keyword	Inductance Bandwidth Packaging Capacitance Silicon Resonance Power systems Impedance Through-silicon vias Wideband
Content Type	Text
Resource Type	Article

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