NDLI: Jitter suppressed on-chip clock distribution using package plane cavity resonance

Content Provider	IEEE Xplore Digital Library
Author	Woojin Lee Chunghyun Ryu Jongbae Park Joungho Kim
Copyright Year	2008
Description	Author affiliation: Dept. of EECS, Korea Adv. Inst. of Sci. & Technol., Daejeon (Woojin Lee; Chunghyun Ryu; Jongbae Park; Joungho Kim)
Abstract	This paper presents a chip-package hybrid clock distribution network using package or PCB plane cavity resonance. This structure enhances Q factor through low loss plane cavity and lowers phase noise. A voltage-controlled oscillator generates clock signal and off-chip driver circuit with the structure of harmonic rejection mixer excites the plane resonance. The plane cavity resonator consists of the embedded planes in package and an inductive load. The resonant frequency can be controlled by the inductance and the various destination points like local buffers can be connected to the plane. We simulate the proposed chip-package co-design with the transmission line matrix modelling and the simulation results show that the source jitter is suppressed by the resonance effect.
Starting Page	427
Ending Page	430
File Size	332383
Page Count	4
File Format	PDF
ISBN	9789810806293
DOI	10.1109/APEMC.2008.4559903
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-19
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Asia Pacific EMC Society
Subject Keyword	Phase noise Transmission line matrix methods Q factor Voltage-controlled oscillators Jitter Packaging Signal generators Resonance Clocks Driver circuits
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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