NDLI: An estimation method of chip level power distribution network inductance using full wave simulation and segmentation method

Content Provider	IEEE Xplore Digital Library
Author	Jaemin Kim Jongjoo Shim Woojin Lee Jun So Pak Joungho Kim
Copyright Year	2008
Description	Author affiliation: Div. of Electr. Eng., KAIST, Daejeon (Jaemin Kim; Jongjoo Shim; Woojin Lee; Jun So Pak; Joungho Kim)
Abstract	An impedance profile of power distribution network (PDN) in system is an efficient criterion to evaluate the system performance in high-speed and high-performance semiconductor system design. Especially, PDN inductance estimation is more important because high impedance occurs at high frequency bandwidth with larger inductance and it generates larger simultaneous switching noise. In this paper, we propose a new calculation method to extract the inductance of chip level PDN based on full wave simulation and segmentation method. We fabricated two kinds of chip level PDN and measured the impedance profiles of test vehicles in the frequency domain up to 20 GHz so as to verify the proposed estimation method.
Starting Page	339
Ending Page	342
File Size	298321
Page Count	4
File Format	PDF
ISBN	9789810806293
DOI	10.1109/APEMC.2008.4559881
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-19
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Asia Pacific EMC Society
Subject Keyword	Semiconductor device noise Inductance Impedance measurement System performance Bandwidth Frequency estimation Power systems Noise generators Frequency measurement Power semiconductor switches
Content Type	Text
Resource Type	Article

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