NDLI: Experimental investigation of the mechanism for CMP micro-scratch formation

Content Provider	IEEE Xplore Digital Library
Author	Aytes, S.D. Armstrong, J.S. Mortensen, K.A. Russell, C.W. Ross, K.A. Giraud, J.E. Hooper, D.H. Alexander, H.M. Corsetti, T.A. Nelson, M.M. Engle, M.W. Prasad, J.
Copyright Year	2003
Description	Author affiliation: AMI Semicond., Pocatello, ID, USA (Aytes, S.D.; Armstrong, J.S.; Mortensen, K.A.; Russell, C.W.; Ross, K.A.; Giraud, J.E.; Hooper, D.H.; Alexander, H.M.; Corsetti, T.A.; Nelson, M.M.; Engle, M.W.; Prasad, J.)
Abstract	CMP (chemical mechanical planarization) micro-scratches are yield and reliability limiting defects in semiconductor production. Electrical shorts, between vias or metal lines, are the most likely failure modes. As device geometries decrease, the probability of a micro-scratch causing a device failure increases. Therefore, understanding of the mechanisms involved in micro-scratch formation becomes increasingly important for good yield and reliability. A mechanism for the formation of micro-scratches and the experimental results in support of the mechanism are presented. It is proposed that micro-scratches are caused primarily by slurry particles that pack into the polish pad fibers during polish (glazing). Once packed into the pad, the silica particles agglomerate. This is especially true if the silica particles are exposed to pH less than ten at the end of the polish or in between polishes. During ex-situ pad conditioning, the agglomerated silica is fractured and loosened from the pad fibers but not removed from the pad surface. The fractured pieces of silica cause micro-scratches, as they break apart during the first few seconds of polish. The experimental data fully support this mechanism. Based on this mechanism, process changes were made producing an order of magnitude reduction in micro-scratch related failures.
Sponsorship	IEEE Electron Devices Soc. Micron Found. IEEE EDS Boise Chapter Boise State Univ
Starting Page	107
Ending Page	109
File Size	179153
Page Count	3
File Format	PDF
ISBN	0780379721
ISSN	07496877
DOI	10.1109/UGIM.2003.1225707
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Slurries Silicon compounds Planarization Dielectrics Contamination Shape Ambient intelligence Semiconductor device reliability Production Information geometry
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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