NDLI: A new architecture for a single-chip multi-channel beamformer based on a standard FPGA

Content Provider	IEEE Xplore Digital Library
Author	Tomov, B.G. Jensen, J.A.
Copyright Year	2001
Description	Author affiliation: Center for Fast Ultrasound Imaging, Tech. Univ. Denmark, Lyngby, Denmark (Tomov, B.G.)
Abstract	A new architecture for a compact medical ultrasound beamformer has been developed. Combination of novel and known principles has been utilized, leading to low processing power requirements and simple analog circuitry. Usage of a field programmable gate array (FPGA) for the digital signal processing provides programming flexibility. First, sparse sample processing is performed by generating the in-phase and quadrature beamformed signals. Hereby only 512 samples are beamformed for each line in an image. That leads to a 15-fold decrease in the number of operations and enables the use of Delta-Sigma (/spl Delta//spl Sigma/) modulation analog-to-digital converters (ADC). Second, simple second-order /spl Delta//spl Sigma/ modulation ADC with classic topology is used. This allows for simple analog circuitry and a very compact design. Several tens of these together with the corresponding preamplifiers can be fitted together onto a single analog integrated circuit. Third, parameter driven delay generation is used, using 3 input parameters per line per channel for either linear array imaging or phased array imaging. The delays are generated on the fly. The delay generation logic also determines the digital apodization by using 2 additional parameters. The control logic consists of few adders and counters and requires very limited resources. Fourth, the beamformer is fully programmable. Any channel can be set to use an arbitrary delay curve, and any number of these channels can be used together in an extendable modular multi-channel system. A prototype of the digital logic is implemented using a Xilinx Virtex-E series FPGA. A 5 MHz center frequency is used along with an oversampling ratio of 14. The sampling clock frequency used is 140 MHz and the number of channels in a single Xilinx 1 million gate FPGA XCV600E is 32. The beamformer utilizes all of the BlockRAM of the device and 33% of its Core Logic Block (CLB) resources. Both simulation results and processed echo data from a phantom are presented.
Sponsorship	Ultrasonics, Ferroelectr., & Frequency Control Soc
Starting Page	1529
Ending Page	1533
File Size	317087
Page Count	5
File Format	PDF
ISBN	0780371771
DOI	10.1109/ULTSYM.2001.992011
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Delay Phased arrays Logic Circuits Delta modulation Frequency Biomedical imaging Ultrasonic imaging Field programmable analog arrays
Content Type	Text
Resource Type	Article

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