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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Youmin Yu Yao, S.A. Sonder Wang Weimin Chen Jiang, Y.W. |
| Copyright Year | 2008 |
| Description | Author affiliation: Freescale Semicond. Inc., Tianjin (Youmin Yu; Yao, S.A.; Sonder Wang; Weimin Chen; Jiang, Y.W.) |
| Abstract | Solder void often is one of main defects when assembling power quad flat no-lead (PQFN) packages. The voids need to be reduced as they are detrimental to package's thermal and mechanical performances. While formation of solder voids is affected by many factors such as solder paste, silicon die backside, lead frame, solder reflow profile, die bonding process, etc., this study focuses on the effects of dispensed solder paste amount on solder void performance. The dispensed solder paste amount is chosen to be investigated as the respective influences of key die bonding parameters such as dispensing time and pressure, bonding time and force all can be reflected by it. The experimental results show that there is an optimal range for the dispensed solder paste amount to reduce solder voids. Either deficient or excessive solder paste amount between power die and lead frame worsens the solder void performance. The solder void characteristics such as void shape, size, distribution, corresponding to different dispensed solder paste amount are different from each other. Those characteristics can be used as guidelines to judge if a dispensed solder paste amount is appropriate to achieve a good solder void performance in actual die bonding process. |
| Starting Page | 896 |
| Ending Page | 900 |
| File Size | 402618 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424417001 |
| ISSN | 10879870 |
| DOI | 10.1109/ITHERM.2008.4544361 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-05-28 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Microassembly Electronic packaging thermal management Semiconductor device packaging Silicon Thermal resistance Lead Soldering Chip scale packaging Temperature distribution Fatigue die attach solder paste amount solder voids |
| Content Type | Text |
| Resource Type | Article |
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