NDLI: Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Content Provider	IEEE Xplore Digital Library
Author	Kokrady, A. Ravikumar, C.P. Chandrachoodan, N.
Copyright Year	2008
Description	Author affiliation: IIT Madras, Chennai (Chandrachoodan, N.) \|\| Texas Instrum. (Kokrady, A.; Ravikumar, C.P.)
Abstract	Debugging memory test failures in a system-on-chip design is becoming difficult due to the growing number and sizes of the embedded memories. Low-complexity marching tests, which are ideally suited for production testing, are insufficient for debug and diagnostics. On-chip support for multiple memory test algorithms can be prohibitively expensive. Moreover, memory test engineers would like the flexibility to make small changes to the test sequence. Run-time programmability can be provided through the use of programmable finite state machines and/or microcode in the BIST controllers. Since such controllers have higher area requirement, it is difficult to employ multiple controllers and distribute them geographically on the chip. Therefore, the BIST controller can become a routing hot-spot. Existing memory BIST insertion flows operate on a post-synthesis net-list and ignore the constraints that will be posed by the physical design step that will follow. These constraints include routing congestion and interconnect timing. Similarly, the synthesis of the BIST logic must also address area, test application time and test power constraints. In this paper, we formulate the problem of programmable memory BIST synthesis as an optimization problem and describe an implementation. Results show upto 3X improvement in area and wirelength for industrial designs when a layout-aware flow is used as opposed to manual BIST implementation.
Starting Page	351
Ending Page	356
File Size	563924
Page Count	6
File Format	PDF
ISBN	9780769533964
ISSN	10817735
DOI	10.1109/ATS.2008.77
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test System-on-a-chip Logic testing Routing Debugging System testing Production Runtime Automata Timing PBIST Test-Time
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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