NDLI: DCScan: A Power-Aware Scan Testing Architecture

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Table of contents

ATS Steering Committee

Program Committee

TTTC Activities Board

ATS 2007 Best Paper Award

Not All Xs are Bad for Scan Compression

Evaluation of Entropy Driven Compression Bounds on Industrial Designs

Untestable Fault Identification in Sequential Circuits Using Model-Checking

A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

LIFTING: A Flexible Open-Source Fault Simulator

Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs

Low-Cost One-Port Approach for Testing Integrated RF Substrates

Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems

Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization

Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns

A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults

Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults

Technique to Improve the Performance of Time-Interleaved A-D Converters with Mismatches of Non-linearity

A Reduced Code Linearity Test Method for Pipelined A/D Converters

Testing LCD Source Driver IC with Built-on-Scribe-Line Test Circuitry

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths

High Quality Pattern Generation for Delay Defects with Functional Sensitized Paths

Refining Delay Test Methodology Using Knowledge of Asymmetric Transition Delay

Effects of Advances in Analog, Mixed Signal and IO Circuits on Test Strategies

Electrical Overstress Prevention & Test Best Practices

Low Distortion Sine Waveform Generation by an AWG

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme

Optimizing Test Data Volume Using Hybrid Compression

Cost Efficient Methods to Improve Performance of Broadcast Scan

Hyperactive Faults Dictionary to Increase Diagnosis Throughput

Enhancing Transition Fault Model for Delay Defect Diagnosis

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis

The HiZ Problem of Power Management IC Testing

Total Jitter Measurement for Testing HSIO Integrated SoCs

Load-Board/PCB Noise Suppression via Electromagnetic Band Gap Power Plane Patterning

Defect Detection Rate through IDDQ for Production Testing

Variation Aware Analysis of Bridging Fault Testing

Prioritizing the Application of DFM Guidelines Based on the Detectability of Systematic Defects

How To Increase the Effectiveness of Yield Diagnostics-Is DFM the Answer to This?

Targeting Leakage Constraints during ATPG

Power Management for Wafer-Level Test During Burn-In

Test Generation for State Retention Logic

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques

On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests

Level-Testability of Multi-operand Adders

System Level LBIST Implementation

CooLBIST: An Effective Approach of Test Power Reduction for LBIST

Practical Challenges in Logic BIST Implementation Case Studies

USB2.0 Logic Built In Self Test Methodology

Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes

Experimental Results of Built-In Jitter Measurement for Gigahertz Clock

Leading Edge Technology and Test Noise

DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits

Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug Method

Detectability of the Two-Dimensional Detector for Time Resolved Emission Measurement

Protocol Aware Test Methodologies Using Today's ATE

Core-Level Compression Technique Selection and SOC Test Architecture Design

Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip

A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC

Accelerated Functional Testing of Digital Microfluidic Biochips

On Reusing Test Access Mechanisms for Debug Data Transfer in SoC Post-Silicon Validation

A Robust Automated Scan Pattern Mismatch Debugger

An Interactive Verification and Debugging Environment by Concrete/Symbolic Simulations for System-Level Designs

Coverage Directed Test Generation: Godson Experience

Test Power Reduction by Blocking Scan Cell Outputs

Two-Gear Low-Power Scan Test

DCScan: A Power-Aware Scan Testing Architecture

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips

A Software-Based Test Methodology for Direct-Mapped Data Cache

Time-Multiplexed Online Checking: A Feasibility Study

On-Line Instruction-Checking in Pipelined Microprocessors

Design of FSM with Concurrent Error Detection Based on Viterbi Decoding

PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Scan Testing in Huffman Coding Test Compression Environment

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing

Power Analysis and Reduction Techniques for Transition Fault Testing

Influence of Parasitic Capacitance Variations on 65 nm and 32 nm Predictive Technology Model SRAM Core-Cells

Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault

GDDR5 Training Challenges and Solutions for ATE-Based Test

A Re-design Technique for Datapath Modules in Error Tolerant Applications

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance

Analyses on Trend of Accidents in Financial Information Systems Reported by Newspapers from the Viewpoint of Dependability

Call for Papers ATS 2009

16th Asian Test Symposium (ATS 2007)

2006 15th Asian Test Symposium

14th Asian Test Symposium (ATS'05)

13th Asian Test Symposium

2003 Test Symposium

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

Proceedings 10th Asian Test Symposium

Proceedings of the Ninth Asian Test Symposium

Proceedings Eighth Asian Test Symposium (ATS'99)

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

Proceedings Sixth Asian Test Symposium (ATS'97)

Proceedings of the Fifth Asian Test Symposium (ATS'96)

Proceedings of the Fourth Asian Test Symposium

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

Proceedings First Asian Test Symposium (ATS `92)

DCScan: A Power-Aware Scan Testing Architecture

Content Provider	IEEE Xplore Digital Library
Author	Gui Dai Zhiqiang You Jishun Kuang Jiedi Huang
Copyright Year	2008
Description	Author affiliation: Coll. of Comput. & Commun., Hunan Univ., Changsha (Gui Dai; Jishun Kuang; Jiedi Huang) \|\| Software Sch., Hunan Univ., Changsha (Zhiqiang You)
Abstract	This paper proposes a novel power-aware scan architecture: DCScan. In this architecture, the compatible scan cells are grouped into the same segment. Test data propagation in DCScan includes two parts: data copying and data shifting. There is no scan shift-in transition during data copying. Experimental results show our approach can achieve low test power, low wiring overhead and low test response data volume.
Starting Page	343
Ending Page	348
File Size	676579
Page Count	6
File Format	PDF
ISBN	9780769533964
ISSN	10817735
DOI	10.1109/ATS.2008.61
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-24
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Power dissipation Wiring Costs Design for testability Software testing Integrated circuit testing Switches Computer architecture Educational institutions compatible scan cells full scan testing low power testing
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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